Dynamic random access memories (hereunder referred to as “DRAM”), a kind of semiconductor memory devices, are mounted in quantity on various electric devices, which we usually use, as main memories of large-scale computers and personal computers and work memories of digital appliances such as mobile phones, digital cameras and the like. Then in accordance with the recent needs for the devices having lower power consumption and higher performances, DRAMs to be mounted on the devices are also required to have higher performances including a lower power, a higher speed and a larger capacity. In particular, the DRAMs mounted on digital appliances are strongly required to have lower power consumption.
One of the most effective means for realizing a DRAM of low power consumption is to operate a memory array at a low data line voltage. By operating a memory array at a low data line voltage, it is possible to remarkably reduce the charge and discharge power dissipation of a data line. In order to operate a DRAM at a low voltage, it is effective to miniaturize a cell transistor and a cell capacitor used for a memory cell of the DRAM. The size of the memory cell can be reduced by the miniaturization. As a result, the length of the data line can be shortened and thus the parasitic capacitance of the data line can be reduced, and therefore low voltage operation can be realized and thus low power consumption can also be realized. Further, since the parasitic capacitance of the data line can be reduced, a high-speed sense amplifier operation can also be realized. Furthermore, since the size of the memory cell is reduced, the capacity of the memory can be increased and thus the device of higher performances can be realized. In this manner, not only the low power but also the miniaturization largely contributes to the realization of higher performances. Hence, it is generally believed that, not only in the case of an existing product but also in the case of a product to be hereafter developed, higher performances, namely lower power consumption and others, are advanced by such miniaturization.
However, as the miniaturization advances up to 65 nm nodes to 45 nm nodes, not only the effect of such higher performances as described above but also various side-effects appear. One of the side-effects is that the miniaturization makes it impossible to secure a memory cell having a sufficiently large capacitance. In the case where a sufficiently large cell capacitance is not secured for example, when a data line voltage VDL is lowered to about 1 V, sometimes the amount of so-called read-out signal voltage of a DRAM may lower and errors may be caused at the time of readout. Further, it sometimes happens that the gate length Lg and the gate width W of a sense amplifier circuit decrease and thus the mismatch of the threshold voltage of the sense amplifier circuit increases, or the gate length Lg and the gate width W of a cell transistor decrease and thus the variation of the threshold voltage of the cell transistor increases, and that causes errors to appear at the time of readout. Therefore, when miniaturization advances, there is the danger that low voltage operation is hardly secured and low power consumption cannot be realized. Such problems are well known as the problems arising when DRAM cells are miniaturized and are precisely described in Kiyoo Itoh, “VLSI Memory Chip Design,” pp. 195-248, Spring, 2001.
As one of the methods for solving the problem of the decrease of the amount of read signals and realizing low voltage operation, there is a means of reducing the number of memory cells connected to one data line and thus shortening the length of the data line. Since the parasitic capacitance of a data line can be reduced by dividing an array and shortening the length of the data line, low voltage operation can be secured. However, as described in Kiyoo Itoh et al., CAS2000, pp. 13-22, October 2000, when an array is merely divided, the area of the chip considerably increases and thus the cost also increases. Further, as described in K. Hieda et al., 1999 IEDM, pp. 289-292, there is a means of applying a high dielectric material such as BST as a dielectric film material used for a cell capacity. However, the material is poor in heat resistance, not consistent with existing DRAM processes, and thus hardly applicable to practical use. Hence, it is desirable to realize a lower voltage by a means not requiring large modification of the processes or addition of a process while inhibiting to the minimum the area of a chip from increasing. As a method for the purpose, there is a means of adding an error correcting code (hereunder referred to as “ECC”) circuit to an array and correcting the information of a bit wrongly read out. As described in JP-A No. 56671/2002 for example, it becomes possible to correct an error bit at the time of readout by adding an ECC circuit to a peripheral circuit section of a DRAM. As a result, correct data can be read out even when miniaturization advances and thus a cell capacity decreases. In other words, in the case where miniaturization advances and a sufficiently large cell capacitance cannot be secured, even when the voltage of a data line is lowered, by using an ECC circuit, stable readout operation can be secured and low power consumption can be realized. Meanwhile, JP-A No. 171199/1989 discloses a means of correcting errors with an ECC circuit during ordinary operation.